#include <bgl_perfctr.h>
#include "papi.h"
#include "papi_internal.h"

native_event_entry_t *native_table=BGL_PERFCTR_event_table;

/* NATIVE PERFCTR API EVENTS */
enum {
        PNE_BGL_FPU_ARITH_ADD_SUBTRACT = 0x40000000,
        PNE_BGL_FPU_ARITH_MULT_DIV,
        PNE_BGL_FPU_ARITH_OEDIPUS_OP,
        PNE_BGL_FPU_ARITH_TRINARY_OP,
        PNE_BGL_FPU_LDST_DBL_LD,
        PNE_BGL_FPU_LDST_DBL_ST,
        PNE_BGL_FPU_LDST_QUAD_LD,
        PNE_BGL_FPU_LDST_QUAD_ST,
        PNE_BGL_2NDFPU_ARITH_ADD_SUBTRACT,
        PNE_BGL_2NDFPU_ARITH_MULT_DIV,
        PNE_BGL_2NDFPU_ARITH_OEDIPUS_OP,
        PNE_BGL_2NDFPU_ARITH_TRINARY_OP,
        PNE_BGL_2NDFPU_LDST_DBL_LD,
        PNE_BGL_2NDFPU_LDST_DBL_ST,
        PNE_BGL_2NDFPU_LDST_QUAD_LD,
        PNE_BGL_2NDFPU_LDST_QUAD_ST,
        PNE_BGL_UPC_L3_CACHE_HIT,
        PNE_BGL_UPC_L3_CACHE_MISS_DATA_ALRDY_WAY_DDR,
        PNE_BGL_UPC_L3_CACHE_MISS_DATA_WILL_BE_REQED_DDR,
        PNE_BGL_UPC_L3_EDRAM_ACCESS_CYCLE,
        PNE_BGL_UPC_L3_EDRAM_RFR_CYCLE,
        PNE_BGL_UPC_L3_LINE_STARTS_EVICT_LINE_NUM_PRESSURE,
        PNE_BGL_UPC_L3_MISS_DIR_SET_DISBL,
        PNE_BGL_UPC_L3_MISS_NO_WAY_SET_AVAIL,
        PNE_BGL_UPC_L3_MISS_REQUIRING_CASTOUT,
        PNE_BGL_UPC_L3_MISS_REQUIRING_REFILL_NO_WR_ALLOC,
        PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ,
        PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ_PLB_RDQ,
        PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ0,
        PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ1,
        PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ_WRBUF,
        PNE_BGL_UPC_L3_PAGE_CLOSE,
        PNE_BGL_UPC_L3_PAGE_OPEN,
        PNE_BGL_UPC_L3_PLB_WRQ_DEP_DBUF,
        PNE_BGL_UPC_L3_PLB_WRQ_DEP_DBUF_HIT,
        PNE_BGL_UPC_L3_PREF_REINS_PULL_OUT_NEXT_LINE,
        PNE_BGL_UPC_L3_PREF_REQ_ACC_BY_PREF_UNIT,
        PNE_BGL_UPC_L3_RD_BURST_1024B_LINE_RD,
        PNE_BGL_UPC_L3_RD_EDR__ALL_KINDS_OF_RD,
        PNE_BGL_UPC_L3_RD_MODIFY_WR_CYCLE_EDR,
        PNE_BGL_UPC_L3_REQ_TKN_CACHE_INHIB_RD_REQ,
        PNE_BGL_UPC_L3_REQ_TKN_CACHE_INHIB_WR,
        PNE_BGL_UPC_L3_REQ_TKN_NEEDS_CASTOUT,
        PNE_BGL_UPC_L3_REQ_TKN_NEEDS_REFILL,
        PNE_BGL_UPC_L3_WRBUF_LINE_ALLOC,
        PNE_BGL_UPC_L3_WRQ0_DEP_DBUF,
        PNE_BGL_UPC_L3_WRQ0_DEP_DBUF_HIT,
        PNE_BGL_UPC_L3_WRQ1_DEP_DBUF,
        PNE_BGL_UPC_L3_WRQ1_DEP_DBUF_HIT,
        PNE_BGL_UPC_L3_WR_EDRAM__INCLUDING_RMW,
        PNE_BGL_UPC_PU0_DCURD_1_RD_PEND,
        PNE_BGL_UPC_PU0_DCURD_2_RD_PEND,
        PNE_BGL_UPC_PU0_DCURD_3_RD_PEND,
        PNE_BGL_UPC_PU0_DCURD_BLIND_REQ,
        PNE_BGL_UPC_PU0_DCURD_COHERENCY_STALL_WAR,
        PNE_BGL_UPC_PU0_DCURD_L3_REQ,
        PNE_BGL_UPC_PU0_DCURD_L3_REQ_PEND,
        PNE_BGL_UPC_PU0_DCURD_LINK_REQ,
        PNE_BGL_UPC_PU0_DCURD_LINK_REQ_PEND,
        PNE_BGL_UPC_PU0_DCURD_LOCK_REQ,
        PNE_BGL_UPC_PU0_DCURD_LOCK_REQ_PEND,
        PNE_BGL_UPC_PU0_DCURD_PLB_REQ,
        PNE_BGL_UPC_PU0_DCURD_PLB_REQ_PEND,
        PNE_BGL_UPC_PU0_DCURD_RD_REQ,
        PNE_BGL_UPC_PU0_DCURD_SRAM_REQ,
        PNE_BGL_UPC_PU0_DCURD_SRAM_REQ_PEND,
        PNE_BGL_UPC_PU0_DCURD_WAIT_L3,
        PNE_BGL_UPC_PU0_DCURD_WAIT_LINK,
        PNE_BGL_UPC_PU0_DCURD_WAIT_LOCK,
        PNE_BGL_UPC_PU0_DCURD_WAIT_PLB,
        PNE_BGL_UPC_PU0_DCURD_WAIT_SRAM,
        PNE_BGL_UPC_PU0_PREF_FILTER_HIT,
        PNE_BGL_UPC_PU0_PREF_PREF_PEND,
        PNE_BGL_UPC_PU0_PREF_REQ_VALID,
        PNE_BGL_UPC_PU0_PREF_SELF_HIT,
        PNE_BGL_UPC_PU0_PREF_SNOOP_HIT_OTHER,
        PNE_BGL_UPC_PU0_PREF_SNOOP_HIT_PLB,
        PNE_BGL_UPC_PU0_PREF_SNOOP_HIT_SAME,
        PNE_BGL_UPC_PU0_PREF_STREAM_HIT,
        PNE_BGL_UPC_PU1_DCURD_1_RD_PEND,
        PNE_BGL_UPC_PU1_DCURD_2_RD_PEND,
        PNE_BGL_UPC_PU1_DCURD_3_RD_PEND,
        PNE_BGL_UPC_PU1_DCURD_BLIND_REQ,
        PNE_BGL_UPC_PU1_DCURD_COHERENCY_STALL_WAR,
        PNE_BGL_UPC_PU1_DCURD_L3_REQ,
        PNE_BGL_UPC_PU1_DCURD_L3_REQ_PEND,
        PNE_BGL_UPC_PU1_DCURD_LINK_REQ,
        PNE_BGL_UPC_PU1_DCURD_LINK_REQ_PEND,
        PNE_BGL_UPC_PU1_DCURD_LOCK_REQ,
        PNE_BGL_UPC_PU1_DCURD_LOCK_REQ_PEND,
        PNE_BGL_UPC_PU1_DCURD_PLB_REQ,
        PNE_BGL_UPC_PU1_DCURD_PLB_REQ_PEND,
        PNE_BGL_UPC_PU1_DCURD_RD_REQ,
        PNE_BGL_UPC_PU1_DCURD_SRAM_REQ,
        PNE_BGL_UPC_PU1_DCURD_SRAM_REQ_PEND,
        PNE_BGL_UPC_PU1_DCURD_WAIT_L3,
        PNE_BGL_UPC_PU1_DCURD_WAIT_LINK,
        PNE_BGL_UPC_PU1_DCURD_WAIT_LOCK,
        PNE_BGL_UPC_PU1_DCURD_WAIT_PLB,
        PNE_BGL_UPC_PU1_DCURD_WAIT_SRAM,
        PNE_BGL_UPC_PU1_PREF_FILTER_HIT,
        PNE_BGL_UPC_PU1_PREF_PREF_PEND,
        PNE_BGL_UPC_PU1_PREF_REQ_VALID,
        PNE_BGL_UPC_PU1_PREF_SELF_HIT,
        PNE_BGL_UPC_PU1_PREF_SNOOP_HIT_OTHER,
        PNE_BGL_UPC_PU1_PREF_SNOOP_HIT_PLB,
        PNE_BGL_UPC_PU1_PREF_SNOOP_HIT_SAME,
        PNE_BGL_UPC_PU1_PREF_STREAM_HIT,
        PNE_BGL_UPC_TI_TESTINT_ERR_EVENT,
        PNE_BGL_UPC_TR_ARB_CH2_VC0_HAVE,
        PNE_BGL_UPC_TR_ARB_CH1_VC0_HAVE,
        PNE_BGL_UPC_TR_ARB_CH0_VC0_HAVE,
        PNE_BGL_UPC_TR_ARB_INJ_VC0_HAVE,
        PNE_BGL_UPC_TR_ARB_CH2_VC1_HAVE,
        PNE_BGL_UPC_TR_ARB_CH1_VC1_HAVE,
        PNE_BGL_UPC_TR_ARB_CH0_VC1_HAVE,
        PNE_BGL_UPC_TR_ARB_INJ_VC1_HAVE,
        PNE_BGL_UPC_TR_ARB_CORE_CH2_VC0_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_CH1_VC0_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_CH0_VC0_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_INJ_VC0_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_CH2_VC1_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_CH1_VC1_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_CH0_VC1_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_INJ_VC1_MATURE,
        PNE_BGL_UPC_TR_ARB_CORE_GREEDY_MODE,
        PNE_BGL_UPC_TR_ARB_CORE_REQ_PEND,
        PNE_BGL_UPC_TR_ARB_CORE_REQ_WAITING_RDY_GO,
        PNE_BGL_UPC_TR_ARB_CLASS0_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS1_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS2_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS3_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS4_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS5_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS6_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS7_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS8_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS9_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS10_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS11_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS12_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS13_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS14_WINS,
        PNE_BGL_UPC_TR_ARB_CLASS15_WINS,
        PNE_BGL_UPC_TR_ARB_SNDR2_BUSY,
        PNE_BGL_UPC_TR_ARB_SNDR1_BUSY,
        PNE_BGL_UPC_TR_ARB_SNDR0_BUSY,
        PNE_BGL_UPC_TR_ARB_LOCAL_CLIENT_BUSY_REC,
        PNE_BGL_UPC_TR_ARB_RCV2_BUSY,
        PNE_BGL_UPC_TR_ARB_RCV1_BUSY,
        PNE_BGL_UPC_TR_ARB_RCV0_BUSY,
        PNE_BGL_UPC_TR_ARB_LOCAL_CLIENT_BUSY_INJ,
        PNE_BGL_UPC_TR_ARB_ALU_BUSY,
        PNE_BGL_UPC_TR_ARB_RCV2_ABORT,
        PNE_BGL_UPC_TR_ARB_RCV1_ABORT,
        PNE_BGL_UPC_TR_ARB_RCV0_ABORT,
        PNE_BGL_UPC_TR_ARB_LOCAL_CLIENT_ABORT,
        PNE_BGL_UPC_TR_ARB_RCV2_PKT_TKN,
        PNE_BGL_UPC_TR_ARB_RCV1_PKT_TKN,
        PNE_BGL_UPC_TR_ARB_RCV0_PKT_TKN,
        PNE_BGL_UPC_TR_ARB_LOCAL_CLIENT_PKT_TKN,
        PNE_BGL_UPC_TR_RCV_0_VC0_DPKT_RCV,
        PNE_BGL_UPC_TR_RCV_0_VC1_DPKT_RCV,
        PNE_BGL_UPC_TR_RCV_0_VC0_EMPTY_PKT,
        PNE_BGL_UPC_TR_RCV_0_VC1_EMPTY_PKT,
        PNE_BGL_UPC_TR_RCV_0_IDLPKT,
        PNE_BGL_UPC_TR_RCV_0_KNOWN_BAD_PKT_MARKER,
        PNE_BGL_UPC_TR_RCV_0_VC0_CUT_THROUGH,
        PNE_BGL_UPC_TR_RCV_0_VC1_CUT_THROUGH,
        PNE_BGL_UPC_TR_RCV_0_VC0_FULL,
        PNE_BGL_UPC_TR_RCV_0_VC1_FULL,
        PNE_BGL_UPC_TR_RCV_0_HDR_PARITY_ERR,
        PNE_BGL_UPC_TR_RCV_0_CRC_ERR,
        PNE_BGL_UPC_TR_RCV_0_UNEXPCT_HDR_ERR,
        PNE_BGL_UPC_TR_RCV_0_RESYNCH_MODE_AFTER_ERR,
        PNE_BGL_UPC_TR_RCV_0_SRAM_ERR_CORR,
        PNE_BGL_UPC_TR_RCV_1_VC0_DPKT_RCV,
        PNE_BGL_UPC_TR_RCV_1_VC1_DPKT_RCV,
        PNE_BGL_UPC_TR_RCV_1_VC0_EMPTY_PKT,
        PNE_BGL_UPC_TR_RCV_1_VC1_EMPTY_PKT,
        PNE_BGL_UPC_TR_RCV_1_IDLPKT,
        PNE_BGL_UPC_TR_RCV_1_KNOWN_BAD_PKT_MARKER,
        PNE_BGL_UPC_TR_RCV_1_VC0_CUT_THROUGH,
        PNE_BGL_UPC_TR_RCV_1_VC1_CUT_THROUGH,
        PNE_BGL_UPC_TR_RCV_1_VC0_FULL,
        PNE_BGL_UPC_TR_RCV_1_VC1_FULL,
        PNE_BGL_UPC_TR_RCV_1_HDR_PARITY_ERR,
        PNE_BGL_UPC_TR_RCV_1_CRC_ERR,
        PNE_BGL_UPC_TR_RCV_1_UNEXPCT_HDR_ERR,
        PNE_BGL_UPC_TR_RCV_1_RESYNCH_MODE_AFTER_ERR,
        PNE_BGL_UPC_TR_RCV_1_SRAM_ERR_CORR,
        PNE_BGL_UPC_TR_RCV_2_VC0_DPKT_RCV,
        PNE_BGL_UPC_TR_RCV_2_VC1_DPKT_RCV,
        PNE_BGL_UPC_TR_RCV_2_VC0_EMPTY_PKT,
        PNE_BGL_UPC_TR_RCV_2_VC1_EMPTY_PKT,
        PNE_BGL_UPC_TR_RCV_2_IDLPKT,
        PNE_BGL_UPC_TR_RCV_2_KNOWN_BAD_PKT_MARKER,
        PNE_BGL_UPC_TR_RCV_2_VC0_CUT_THROUGH,
        PNE_BGL_UPC_TR_RCV_2_VC1_CUT_THROUGH,
        PNE_BGL_UPC_TR_RCV_2_VC0_FULL,
        PNE_BGL_UPC_TR_RCV_2_VC1_FULL,
        PNE_BGL_UPC_TR_RCV_2_HDR_PARITY_ERR,
        PNE_BGL_UPC_TR_RCV_2_CRC_ERR,
        PNE_BGL_UPC_TR_RCV_2_UNEXPCT_HDR_ERR,
        PNE_BGL_UPC_TR_RCV_2_RESYNCH_MODE_AFTER_ERR,
        PNE_BGL_UPC_TR_RCV_2_SRAM_ERR_CORR,
        PNE_BGL_UPC_TR_SNDR_0_VC0_EMPTY,
        PNE_BGL_UPC_TR_SNDR_0_VC1_EMPTY,
        PNE_BGL_UPC_TR_SNDR_0_VC0_CUT_THROUGH,
        PNE_BGL_UPC_TR_SNDR_0_VC1_CUT_THROUGH,
        PNE_BGL_UPC_TR_SNDR_0_VC0_PKT_SENT_TOTAL,
        PNE_BGL_UPC_TR_SNDR_0_VC1_PKT_SENT_TOTAL,
        PNE_BGL_UPC_TR_SNDR_0_VC0_DPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_0_VC1_DPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_0_IDLPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_0_RESEND_ATTS,
        PNE_BGL_UPC_TR_SNDR_0_SRAM_ERR_CORR,
        PNE_BGL_UPC_TR_SNDR_1_VC0_EMPTY,
        PNE_BGL_UPC_TR_SNDR_1_VC1_EMPTY,
        PNE_BGL_UPC_TR_SNDR_1_VC0_CUT_THROUGH,
        PNE_BGL_UPC_TR_SNDR_1_VC1_CUT_THROUGH,
        PNE_BGL_UPC_TR_SNDR_1_VC0_PKT_SENT_TOTAL,
        PNE_BGL_UPC_TR_SNDR_1_VC1_PKT_SENT_TOTAL,
        PNE_BGL_UPC_TR_SNDR_1_VC0_DPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_1_VC1_DPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_1_IDLPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_1_RESEND_ATTS,
        PNE_BGL_UPC_TR_SNDR_1_SRAM_ERR_CORR,
        PNE_BGL_UPC_TR_SNDR_2_VC0_EMPTY,
        PNE_BGL_UPC_TR_SNDR_2_VC1_EMPTY,
        PNE_BGL_UPC_TR_SNDR_2_VC0_CUT_THROUGH,
        PNE_BGL_UPC_TR_SNDR_2_VC1_CUT_THROUGH,
        PNE_BGL_UPC_TR_SNDR_2_VC0_PKT_SENT_TOTAL,
        PNE_BGL_UPC_TR_SNDR_2_VC1_PKT_SENT_TOTAL,
        PNE_BGL_UPC_TR_SNDR_2_VC0_DPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_2_VC1_DPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_2_IDLPKTS_SENT,
        PNE_BGL_UPC_TR_SNDR_2_RESEND_ATTS,
        PNE_BGL_UPC_TR_SNDR_2_SRAM_ERR_CORR,
        PNE_BGL_UPC_TR_INJ_VC0_HDR_ADDED,
        PNE_BGL_UPC_TR_INJ_VC1_HDR_ADDED,
        PNE_BGL_UPC_TR_INJ_VC0_PYLD_ADDED,
        PNE_BGL_UPC_TR_INJ_VC1_PYLD_ADDED,
        PNE_BGL_UPC_TR_INJ_VC0_PKT_TKN,
        PNE_BGL_UPC_TR_INJ_VC1_PKT_TKN,
        PNE_BGL_UPC_TR_INJ_SRAM_ERR_CORR,
        PNE_BGL_UPC_TR_REC_VC0_PKT_ADDED,
        PNE_BGL_UPC_TR_REC_VC1_PKT_ADDED,
        PNE_BGL_UPC_TR_REC_VC0_HDR_TKN,
        PNE_BGL_UPC_TR_REC_VC1_HDR_TKN,
        PNE_BGL_UPC_TR_REC_VC0_PYLD_TKN,
        PNE_BGL_UPC_TR_REC_VC1_PYLD_TKN,
        PNE_BGL_UPC_TR_REC_VC0_PKT_DISC,
        PNE_BGL_UPC_TR_REC_VC1_PKT_DISC,
        PNE_BGL_UPC_TR_REC_SRAM_ERR_CORR,
        PNE_BGL_UPC_TS_XM_32B_CHUNKS,
        PNE_BGL_UPC_TS_XM_ACKS,
        PNE_BGL_UPC_TS_XM_LINK_AVAIL_NO_VCBN_TOKENS,
        PNE_BGL_UPC_TS_XM_LINK_AVAIL_NO_VCBP_TOKENS,
        PNE_BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD1_TOKENS,
        PNE_BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS,
        PNE_BGL_UPC_TS_XM_PKTS,
        PNE_BGL_UPC_TS_XM_TOKEN_ACKS,
        PNE_BGL_UPC_TS_XM_VCBN_CHUNKS,
        PNE_BGL_UPC_TS_XM_VCBP_CHUNKS,
        PNE_BGL_UPC_TS_XM_VCD0_CHUNKS,
        PNE_BGL_UPC_TS_XM_VCD1_CHUNKS,
        PNE_BGL_UPC_TS_XP_32B_CHUNKS,
        PNE_BGL_UPC_TS_XP_ACKS,
        PNE_BGL_UPC_TS_XP_LINK_AVAIL_NO_VCBN_TOKENS,
        PNE_BGL_UPC_TS_XP_LINK_AVAIL_NO_VCBP_TOKENS,
        PNE_BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD1_TOKENS,
        PNE_BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS,
        PNE_BGL_UPC_TS_XP_PKTS,
        PNE_BGL_UPC_TS_XP_TOKEN_ACKS,
        PNE_BGL_UPC_TS_XP_VCBN_CHUNKS,
        PNE_BGL_UPC_TS_XP_VCBP_CHUNKS,
        PNE_BGL_UPC_TS_XP_VCD0_CHUNKS,
        PNE_BGL_UPC_TS_XP_VCD1_CHUNKS,
        PNE_BGL_UPC_TS_YM_32B_CHUNKS,
        PNE_BGL_UPC_TS_YM_ACKS,
        PNE_BGL_UPC_TS_YM_LINK_AVAIL_NO_VCBN_TOKENS,
        PNE_BGL_UPC_TS_YM_LINK_AVAIL_NO_VCBP_TOKENS,
        PNE_BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD1_TOKENS,
        PNE_BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS,
        PNE_BGL_UPC_TS_YM_PKTS,
        PNE_BGL_UPC_TS_YM_TOKEN_ACKS,
        PNE_BGL_UPC_TS_YM_VCBN_CHUNKS,
        PNE_BGL_UPC_TS_YM_VCBP_CHUNKS,
        PNE_BGL_UPC_TS_YM_VCD0_CHUNKS,
        PNE_BGL_UPC_TS_YM_VCD1_CHUNKS,
        PNE_BGL_UPC_TS_YP_32B_CHUNKS,
        PNE_BGL_UPC_TS_YP_ACKS,
        PNE_BGL_UPC_TS_YP_LINK_AVAIL_NO_VCBN_TOKENS,
        PNE_BGL_UPC_TS_YP_LINK_AVAIL_NO_VCBP_TOKENS,
        PNE_BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD1_TOKENS,
        PNE_BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS,
        PNE_BGL_UPC_TS_YP_PKTS,
        PNE_BGL_UPC_TS_YP_TOKEN_ACKS,
        PNE_BGL_UPC_TS_YP_VCBN_CHUNKS,
        PNE_BGL_UPC_TS_YP_VCBP_CHUNKS,
        PNE_BGL_UPC_TS_YP_VCD0_CHUNKS,
        PNE_BGL_UPC_TS_YP_VCD1_CHUNKS,
        PNE_BGL_UPC_TS_ZM_32B_CHUNKS,
        PNE_BGL_UPC_TS_ZM_ACKS,
        PNE_BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCBN_TOKENS,
        PNE_BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCBP_TOKENS,
        PNE_BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD1_TOKENS,
        PNE_BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS,
        PNE_BGL_UPC_TS_ZM_PKTS,
        PNE_BGL_UPC_TS_ZM_TOKEN_ACKS,
        PNE_BGL_UPC_TS_ZM_VCBN_CHUNKS,
        PNE_BGL_UPC_TS_ZM_VCBP_CHUNKS,
        PNE_BGL_UPC_TS_ZM_VCD0_CHUNKS,
        PNE_BGL_UPC_TS_ZM_VCD1_CHUNKS,
        PNE_BGL_UPC_TS_ZP_32B_CHUNKS,
        PNE_BGL_UPC_TS_ZP_ACKS,
        PNE_BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCBN_TOKENS,
        PNE_BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCBP_TOKENS,
        PNE_BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD1_TOKENS,
        PNE_BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS,
        PNE_BGL_UPC_TS_ZP_PKTS,
        PNE_BGL_UPC_TS_ZP_TOKEN_ACKS,
        PNE_BGL_UPC_TS_ZP_VCBN_CHUNKS,
        PNE_BGL_UPC_TS_ZP_VCBP_CHUNKS,
        PNE_BGL_UPC_TS_ZP_VCD0_CHUNKS,
        PNE_BGL_UPC_TS_ZP_VCD1_CHUNKS,
        PNE_BGL_PERFCTR_NULL_EVENT,
		PNE_BGL_PAPI_TIMEBASE
};

/* PAPI PRESETS */
const hwi_search_t _papi_hwd_bgl_preset_map[] = {
  /* total l3 interactions */
  {PAPI_L3_TCM, {0,
                {PNE_BGL_UPC_L3_CACHE_MISS_DATA_WILL_BE_REQED_DDR | EDGE_RISE, 
                 PAPI_NULL},{0,}}},

  /* l3 load miss (derived) */ 
  {PAPI_L3_LDM, {DERIVED_ADD, 
                {PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ0 | EDGE_RISE, 
                 PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ_RDQ1 | EDGE_RISE, 
                 PAPI_NULL, PAPI_NULL}, {0,}}},

  /* l3 store miss */
  {PAPI_L3_STM, {0,
                {PNE_BGL_UPC_L3_MSHNDLR_TOOK_REQ_WRBUF | EDGE_RISE, 
                 PAPI_NULL},{0,}}},

  /* fma instructions completed */
  {PAPI_FMA_INS, {0,
                 {PNE_BGL_FPU_ARITH_TRINARY_OP | EDGE_HI, 
                  PAPI_NULL},{0,}}},

  /* total cycles */
  {PAPI_TOT_CYC, {0,
                 {BGL_PAPI_TIMEBASE | EDGE_HI, 
                  PAPI_NULL},{0,}}},

  /* l2 data cache hit (derived) */
  {PAPI_L2_DCH, {DERIVED_ADD, 
                {PNE_BGL_UPC_PU0_PREF_STREAM_HIT | EDGE_RISE, 
                 PNE_BGL_UPC_PU1_PREF_STREAM_HIT | EDGE_RISE, 
                 PAPI_NULL, PAPI_NULL}, {0,}}}, 

  /* l2 data cache access (derived) */
  {PAPI_L2_DCA, {DERIVED_ADD,
                {PNE_BGL_UPC_PU0_PREF_REQ_VALID | EDGE_RISE, 
                 PNE_BGL_UPC_PU1_PREF_REQ_VALID | EDGE_RISE, 
                 PAPI_NULL, PAPI_NULL},{0,}}},

  /* l3 total cache hits */
  {PAPI_L3_TCH, {0,
                {PNE_BGL_UPC_L3_CACHE_HIT | EDGE_RISE, 
                 PAPI_NULL},{0,}}},

  /* floating point multiply instructions */
  {PAPI_FML_INS, {0, 
                 {PNE_BGL_FPU_ARITH_MULT_DIV | EDGE_HI, 
                  PAPI_NULL}, {0,}}},

  /* floating point add instructions */
  {PAPI_FAD_INS, {0, 
                 {PNE_BGL_FPU_ARITH_ADD_SUBTRACT | EDGE_HI, 
                  PAPI_NULL}, {0,}}},

  /* oedipus operations (bgl specific) */
  {PAPI_BGL_OED, {0,
                 {PNE_BGL_FPU_ARITH_OEDIPUS_OP | EDGE_HI, 
                  PAPI_NULL},{0,}}},

  /* torus 32B chunks sent (derived, bgl specific) */
  {PAPI_BGL_TS_32B, {DERIVED_ADD, 
                    {PNE_BGL_UPC_TS_XM_32B_CHUNKS | EDGE_RISE, 
                     PNE_BGL_UPC_TS_XP_32B_CHUNKS | EDGE_RISE, 
                     PNE_BGL_UPC_TS_YM_32B_CHUNKS | EDGE_RISE, 
                     PNE_BGL_UPC_TS_YP_32B_CHUNKS | EDGE_RISE, 
                     PNE_BGL_UPC_TS_ZM_32B_CHUNKS | EDGE_RISE, 
                     PNE_BGL_UPC_TS_ZP_32B_CHUNKS | EDGE_RISE, 
                     PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL},{0,}}},

  /* torus no token upc cycles (derived, bgl specific) */
  {PAPI_BGL_TS_FULL, {DERIVED_ADD, 
                     {PNE_BGL_UPC_TS_XM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS | EDGE_HI, 
                      PNE_BGL_UPC_TS_XP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS | EDGE_HI, 
                      PNE_BGL_UPC_TS_YM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS | EDGE_HI, 
                      PNE_BGL_UPC_TS_YP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS | EDGE_HI, 
                      PNE_BGL_UPC_TS_ZM_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS | EDGE_HI, 
                      PNE_BGL_UPC_TS_ZP_LINK_AVAIL_NO_VCD0_VCD_VCBN_TOKENS | EDGE_HI, 
                      PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL},{0,}}}, 

  /* tree 256 byte packets (derived, bgl specific) */
  {PAPI_BGL_TR_DPKT, {DERIVED_ADD,
                     {PNE_BGL_UPC_TR_SNDR_2_VC1_DPKTS_SENT | EDGE_RISE,
                      PNE_BGL_UPC_TR_SNDR_2_VC0_DPKTS_SENT | EDGE_RISE,
                      PNE_BGL_UPC_TR_SNDR_1_VC1_DPKTS_SENT | EDGE_RISE,
                      PNE_BGL_UPC_TR_SNDR_1_VC0_DPKTS_SENT | EDGE_RISE,
                      PNE_BGL_UPC_TR_SNDR_0_VC1_DPKTS_SENT | EDGE_RISE,
                      PNE_BGL_UPC_TR_SNDR_0_VC0_DPKTS_SENT | EDGE_RISE,
                      PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL},{0,}}},

  /* upc cycles (clockx2) tree rcv is full (derived, bgl specific) */
  {PAPI_BGL_TR_FULL, {DERIVED_ADD,
                     {PNE_BGL_UPC_TR_RCV_0_VC0_FULL | EDGE_HI,
                      PNE_BGL_UPC_TR_RCV_0_VC1_FULL | EDGE_HI,
                      PNE_BGL_UPC_TR_RCV_1_VC0_FULL | EDGE_HI,
                      PNE_BGL_UPC_TR_RCV_1_VC1_FULL | EDGE_HI,
                      PNE_BGL_UPC_TR_RCV_2_VC0_FULL | EDGE_HI,
                      PNE_BGL_UPC_TR_RCV_2_VC1_FULL | EDGE_HI,
                      PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL, PAPI_NULL},{0,}}},

  /* papi null */
  {0, {0, {PAPI_NULL, PAPI_NULL}, {0,}}}
};
 
inline void get_bgl_native_event(int Event, BGL_PERFCTR_event_t *ret)
{
  int count;
/*  BGL_PERFCTR_event_t ret;*/

  ret->num = -1;
  ret->edge = -1;

  /* strip out edge info and store seperately */
  count = (Event & 0x30000000) >> 28;
  Event = Event & 0x4FFFFFFF;
  ret->edge = count;

  if(Event == PNE_BGL_PAPI_TIMEBASE)
    ret->num = BGL_PAPI_TIMEBASE;
  else if(Event < PNE_BGL_PAPI_TIMEBASE)
    ret->num = Event & PAPI_NATIVE_AND_MASK;

/*  default:
    ret->num = -1;
    ret->edge = -1;
*/
}


